SoC Design Engineer

Job description

Job Description
In this job the Candidate shall be resposible for EITHER of the description below : You will be part of STA and timing closure activities of Intel SoCs. Your tasks may include but not limited to Understanding of Design, Architecture and Clocking, Interaction with FE/DFT/Verification teams, Understanding of constraints, synchronous & asynchronous paths, Clock domain crossing issues, Timing closure, generating timing ECOs Timing signoff & Debugging/troubleshooting of timing issues in a design. You will be part of Physical Sign-Off Verification Team and resolve problems related to DRC, LVS, ERC, FC Integration and TapeOut. You would be needed to work both at partition as well as FC Level. You would be participating in any activities related to methodology development in Physical Verification Domain. You will be part of LEC/LP Sign-Off Team. You would be reponsible for debugging complex issues related to LEC and Low Power both at partition level and SoC. Additional experience in Low Power Logical Equivalence is added advantage. You shall be part of the Power Delivery team where you shall be part of the team defining the Power Grid for a complex SoC. You shall be responsible to Sign-Off the SoC for IR Checks Vectored or Vectorless which includes Static, Dynamic, Ramp-up Analysis. The need would be both at partition level as well at SoC Level. You will be part of Power Estimation team where besides estimation you shall be needed to drive state-of-art Power Optimisation methodologies to reduce overall dynamic/leakage power for SoC.Additional skills include: - Hands-On experience with domain relevant industry standard tools like ICC, Primetime, Redhawk, ICV, Calibre, Conformal, Spyglass-LP, Power Artist Etc.- Good understanding and exposure of overall SoC Cycle. - Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies.- You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

Qualifications

You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering with 3 upto 9 years of relevant experience with the skills in all/either Physical Implementation,Timing Closure, LEC, PDN Low Power Verification or Physical Verification .