Sr. Signal Integrity Engineer

Job description

DESCRIPTION

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team.
The team is responsible for all the physical interfaces of the device, from their electrical and hardware usage perspective. This includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes. Last but not least, the team is also carrying lab work for in-depth electrical characterization of the interfaces and coming up with support software tools for debug and diagnostics.
As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration to the Die, through SI/PI simulation and package layout through reference board design aspects and hands-on lab characterization.
This position is for an experienced engineer with strong background in Silicon-Validation \ Electrical-Simulations \ Board Design, to take on all aspects of the devices electrical interfaces throughout the whole SoC design stages.

PREFERRED QUALIFICATIONS

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team.

Desired profile

BASIC QUALIFICATIONS

· BSc in Electrical Engineering.
· 5-10 year work experience
· Multidisciplinary background in at least two of the following (Chip Physical Implementation\Package design\Board Design\Silicon Electrical Validation).
· Strong analytical and problem-solving skills with a proven track record of hands-on lab experience.
· Experienced in high-speed digital interfaces such as modern memories and SerDes.
· Experienced in Electrical simulations using HSPICE is an advantage.
· Excellent written and verbal communication skills (mainly English)
· Great teammate skills