Associate Profesor
- Maintenant
Enrique Villa
Sr. PCB Design Engineer
41 ans • Guadalajara
Résumé
As a team player in the industry, and actively participating in education. I understand the importance of properly share the knowledge to everyone, so we can all learn from each other and participate in the growth of a better society.
Compétences
Expériences
Sr. PCB Design Engineer
- MaintenantEnergie / Matériaux / Mécanique Expertise in 2L to 8L printed circuit board design for instrument & display clusters. Experience working with low-speed signal routing finding a balance between low-layer-count, signal integrity requirement, reducing EMC radiation, improving EMC immunity, and DFX. Experience working with switching regulator power supplies implementing very small return loops to avoid electromagnetic emissions.
Interaction with EMC and SI specialist to properly implement placement/routing solutions for different customers. Experience using Nextra CAD tool to perform collision checks during project execution. Maintenance of PCB Assemblies in current projects around the world in collaboration with other site locations (like China and Germany), using SAP-NPP.
Analog Engi
- Conception / Génie civil / Génie industriel Experience in performing signal integrity analysis on DDR4 high-speed interconnection: 2D transmission line models and stack-up definition, transient simulations using Hspice, statistical analysis using JMP for worst case analysis.
Signal Integrity Engineer
- Conception / Génie civil / Génie industriel Experience in signal integrity analysis: high-speed and high-density multilayer server base boards, memory riser boards, and back-plane boards for Xeon processors.
Responsible of the signal integrity analysis, have gone through simulation and measurement of RGMII/RMII; and also design review cycles of DDR3/DDR4 signals for Xeon processors.
Have participated in the stack-up definition of multilayer boards: impedance control, material losses for high-speed signals, etc.
Sr. PCB Design Engineer
- Conception / Génie civil / Génie industriel Experience on high-speed/density multilayer 4S/2S boards, and memory riser boards, in the server/workstation markets. Have gone through the development of reference designs for Sandy-Bridge-based Xeon and Haswell-based Xeon families. Technical expertise leading layout activities.
Experience leading the Layout effort to negotiate solutions that better integrates feedback from Hardware, Architecture, Manufacturing, Tests, System Mechanical, Interconnect Simulation, Power Integrity, Package teams, and clients, among others.
Experience using Cadence PCB Editor, Constraint Manager: placement and routing of high-speed interfaces, voltage regulators, test points, breakout and pin out definition, among others.
Internship
- Conception / Génie civil / Génie industriel Experience on documentation, generated manual/user guide for Cadence Allegro 15.0: Library Creation, Schematic Creation, PCB Editor, and Constraint Manager usage.
Formations
ITESO
2007 - 2013 Conception / Génie civil / Génie industriel Thesis: Parameter extraction methodology for composite right/left-handed transmission lines using quasi-static models
Centro De Tecnologia Y Semiconductores
2006 - 2007 Energie / Matériaux / Mécanique Experience using Mentor Graphics DxDesigner and Expedition, gone through a training design phase, schematic capture, library creation/maintenance, understanding mechanical/placement requirements, routing rules, PCB stack-up, bill of materials, and document/gerber generation. Trainee on Design for Manufacture, High-Speed, and some IPC, EMI, and ESD highlights.
INSTITUTO TECNOLOGICO DE HERMOSILLO
2001 - 2006 Energie / Matériaux / Mécanique I participated in folloiwng contests:
-line following robot
-mechatronics regional contest
Mes qualités
Langues parlées
Anglais Professionnel Espagnol Langue maternelle
Mes souhaits
Be a fundamental part of new technology creation