Barindra Ghosh

8+ years experience in ASIC verification. Functional verification at IP, sub-system level and SoC level for multi-million(~80) complex SOCs in semiconductor Industry. Specialties: Hands on knowledge of developing verification environment architecture for SoC/Subsystem/IP level functional verification & validation(simulation acceleration) using Verilog and System Verilog using UVM and OVM. Worked on protocols :: PCIe 3.0, SAS, SATA, NVMe, AXI, PLB, JTAG, SPI, AMBA, SDB, GPIO, UART, DFx and MDIO etc. ***Expertise in Architecting Test Environment with SV with UVM. *** Development of Verification environments and components(UVC, VIP, RAL ) using SV with UVM/OVM. ***Completed certified OVM System Verilog training from Cadence. ***Unit level and System level verification of complex IPs, SoCs and ASICs ***Pursued a competent M.Tech in VLSI design and Microelectronics Technology from ETCE department of Jadavpur University. GOALS :: To pursue a challenging and satisfying career in Semiconductor(VLSI) field and be a part of a progressive organization that gives me a scope to enhance my knowledge and skills in order to cope with the latest technological changes.