Offers “Station F”

Expires soon Station F

Design Verification Engineer F/H

  • Internship
  • Grenoble (Isère)
  • Design / Civil engineering / Industrial engineering

Job description



About

UPMEM is a fabless semiconductor company that provides world leading silicon based Processing In-Memory (PIM) technology and solutions. Our unique PIM solutions accelerate 20x data intensive applications in the datacenter while being 10x more energy efficient. UPMEM solves the memory bottleneck and reduces the data movement dominant energy cost of the computing node by cutting drastically off-chip data movement. UPMEM PIM is the 1st efficient scalable programmable acceleration solution readily to be integrated in application servers in datacenter for data-intensive apps such as genomics, AI, analytics, search.
With the first products being delivered to early customers, UPMEM is offering mature PIM solutions to its worldwide customers who are seeking for big data applications processing acceleration solutions.

Job Description

Au sein de l’équipe Hardware Design, vous participez au développement de nos futures générations de circuits intégrés.
Notamment, vous serez impliqué dans le design et la vérification fonctionnelle du circuit :

·  Architecture et μ-architecture des différents composants du circuit (processeur, DMA, interface x86, interface mémoire),
·  Définition et écriture des modèles de référence,
·  Mise en place des plateformes de vérification (SoC, IPs) et écriture/gestion de tests système,
·  Définition des règles ou propriétés et mesure de la couverture fonctionnelle.

Job description
As Hardware Design team member, you will participate to the development of our next generation solutions.
You will be involved in design and functionnal verification of the chips:

·  Architecture and μ-architecture of the different modules of the chip (processor, DMA, x86 interface, memory interface),
·  Définition and development of reference models,
·  Setup of verification platforms and testbenches (SoC, IPs) then tests development
·  Definition of rules and functionnal coverage measurement.

Preferred Experience

Une expérience d’au moins 5 ans dans les domaines suivants vous est demandée :

·  Vérification fonctionnelle (UVM, VIP),
·  Codage RTL et vérification (VHDL, Verilog, SystemVerilog, PSL)

Grande aisance à évoluer à l’écrit et l’oral en anglais dans une équipe et un environnement international,
Environnement unix (shell, git, ...),

La connaissances des architecture et μ-architecture des processeurs serait un plus.

Qualités recherchées
Rapide, autonome, rigoureux, vous aimez adresser des problèmes complexes et nouveaux. Vous mettez un accent particulier sur la qualité de votre travail, sa fiabilité et sa maintenabilité.
Vous aimez travailler en équipe, partager la connaissance, échanger les idées.

* Skills and experience *
MS in electrical engineering or related field
5+ years of relevant experiences in the following domains:

·  Functionnal verification (UVM, VIP),
·  RTL coding and verification (VHDL, Verilog, SystemVerilog, PSL)

Great oral and written communication and presentation skills in English
Unix environment (shell, git, ...),

Processors architecture & μ-architecture knowledge would be appreciated.

* Expected qualities *
Autonomous, you feel confortable in a very fast-paced and continuously changing environment.
You have a specific focus on your work quality, reliability and maintainability.
Open-Minded, accountable, Empathetic, Collaborative

Recruitment Process

CV + lettre de motivation, puis 2 entretiens
CV + letter, followed by 2 meetings

Additional Information

·  Contract Type: Full-Time
·  Location: Grenoble, France (38000)
·  Education Level: Master's Degree
·  Experience: > 4 years

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