Similar Jobs SOC IP Logic Engineer Servers

Job description

Job Description

As a Logic Design Engineer, you will be working as a part of the IP design team within the Scalable performance CPU Development Group, working on next-generation Xeon products/IPs for Server markets in high performance coherency fabrics.

Responsibilities

·  All phases of front-end architecture and design:
·  Micro-architectural design and specification
·  Working with architects on feature scoping and approvals
·  feasibility studies
·  Logic design
·  Integration of third party IPs
·  Engage in activities ranging from Architecture development and design trade-off analysis, RTL coding, and creating specification documents
·  Test-plan generation, design reviews, timing analysis, ECOs, and post silicon debug
·  Close collaboration with planning teams, architects, and validation and physical design teams will be required
·  Provide IP integration support to SoC customers

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Desired profile

Qualifications

·  BS degree in Electrical Engineering, Computer Engineering or other related field of study with 4+ years of relevant experience in SOC/IP logic design or MS degree with 3+ years or PHD with 1+ years of direct related experience with SOC logic design andintegration
·  Experience with logic design using Verilog or similar Register Transfer Language
·  Experience working with verification and structural design teams

Preferred

·  Experience with System Verilog and OVM
·  Experience with cache coherency protocols
·  Experience with scripting languages