Hardware Engineer - SOC Design Lead

Job description

Job Description

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara

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Desired profile

Qualifications

You will be part of Intel's Programmable Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes.

Responsibilities include the following:

·  Integration of complex IP's, which requires in-depth knowledge of security IP: MACsec, IPsec.
·  Tasks include authoring detailed functional spec, microarchitecture spec, developing surrounding logic, integration and optimization of any memories and hard macros required, and writing timing constraints.
·  RTL and constraint quality checks, including lint, CDC, Fishtail.Contribute to chip-level integration: interface definition, clock/reset architecture, RTL, timing constraints integration
·  Development, assessment, and refinement of RTL design to target power, performance, area and timing goals.
·  Working with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.
·  Support IP, subsystem, and full-chip level verification by providing design requirements, review verification plan, functional/code coverage results, and simulation debug.
·  Power state definition and management Dynamic clocking solutions Clock generation and asynchronous clock crossing strategies
·  Work with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs
·  Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.

Qualifications:

·  BS or MS in electrical engineering or computer science
·  5+ years of experience in high performance digital logic designs and integration
·  2+ years of experience with synthesis, static timing analysis
·  Hands-on experience with security protocols strongly preferred
·  Prior experience in Design for Debug/Test, including ATPG, MBIST, LBIST, strongly preferred
·  Good verbal and written communication skills