Similar Jobs Physical Design Engineer

Job description

Job Description

Independently Creates Block Level Layout ensuring quality & schedule of deliverablesHas Skills to do floorplan, power grid templates, device placements for matching etcUnderstand Design Specifications to to good routing to reduce parasitics, match routes, meet signal RV specs etc..Be proficient in Cadence Virtuoso on 10nm and below and/or Intel Genesys Layout toolMust have good expertize in Layout verification tools like Synopsys ICV and troubleshoot a wide variety of LV errors up to and including LVS, DRC, Antenna, Density, DFM etc for 10nm and belowGood understanding of RV, ESD, LatchupMust possess good communication skills to work with Circuit Design Engineer to identify tasks, do planning and scheduling of the deliverables for the block he/she ownsUnderstanding of basic circuits like gates, opamps, driver/pre-driver etc..

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

Qualifications

BE/BTech with 2+ yrs of experience in Analog Layout design, must have worked on designing layouts for IPs like PCIe, USB Type-C, High Speed SerDes, MIPI DPHY/CPHY, DisplayPort/HDMI, DDRs, PLLs etc