Layout vs Schematic and Parasitic Extraction Engineer

Job description

Job Title: Layout vs Schematic (LVS) and Parasitic Extraction Engineer
Preferred Locations: (Austin, TX, Cambridge, MA, Albany, NY, San Jose, CA and Yorktown, NY)

Be part of a dynamic and skilled IBM Research team developing design enablement for the world's most advanced semiconductor technologies. Develop Layout vs Schematic (LVS) and Parasitic Extraction (PEX) decks using industry-standard tools such as Mentor Graphics’ Calibre and Synopsys Star-RCXT. Close and frequent cooperation with process development engineers will be required.

Auto req ID

149851BR
Required Education

Bachelor's Degree
Role ( Job Role )

Semiconductor Manufacturing Engineering Prof
State / Province

NEW YORK
Primary job category

Manufacturing
Company

(0147) International Business Machines Corporation
Contract type

Regular
Employment Type

Full-Time
Is this role a commissionable/sales incentive based position?

No
Travel Required

Up to 10% or 1 day a week
IBM Business Group

Research
Preferred Education

Master's Degree
City / Township / Village

ALBANY
EO Statement

IBM is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Required Technical and Professional Expertise

Required Skills
·  Layout vs Schematic (LVS) deck development with Mentor Graphics’ Calibre or Synopsys ICV - 3 years
·  Parasitic Extraction (PEX) deck development with Synopsys StarRCXT or another industry-standard tool - 3 years.
·  Understanding of physical layout, technology groundrules, and semiconductor processing - 3 years
·  Experience developing automation and scripting - 2 years.
·  Experience using the Cadence Virtuoso or other layout design tool.
·  Ability to debug errors and solve problems.
·  Ability to work in a team environment.
·  Fluent English (both verbal and written) and strong communication skills.
Country/Region

United States
Preferred Technical and Professional Experience

Preferred

·  Experience with advanced sub-micron semiconductor technology nodes.
·  Experience with both LVS and PEX.
Eligibility Requirements

None
Position Type

Professional
New Collar Role

No