- Energie / Matériaux / MécaniqueDevelop verification environments of Bull-ASICs (application specific integrated circuit) Control/Status Register (CSR) according to the Universal Verification Methodology(UVM).
- Development of UVM testbenchs.
- Vertical and horizontal reuse.
- Elaboration of verification sequences.
- Automating the generation of the verification environment.
- Analysis of predefined UVM tests.
- Writing bug reports.
- Scripting.
- Debugging.
- Tools : Synopsys-VCS, SystemVerilog, UVM, Python.
IP Verification Engineer (PFE)
- Energie / Matériaux / MécaniqueDevelop verification environments of digital IPs (Intellectual property) ST/Imaging dedicated to Mobile platforms.
- Development of UVM testbenchs.
- Vertical and horizontal reuse.
- Elaboration of verification sequences and Checkers.
- Elaboration of a functional cover model.
- Generating a scoreboard agent.
- Debugging.
- Tools : Cadence-Incisive, SystemVerilog, UVM.